Search Jobs
Hardware Design Engineer 5 - HW Design Verification Eng.
3009 158th Place Northeast Redmond, WA 98052 US
Job Description
Position Description: Protingent has an exciting contract opportunity for a Hardware Design Engineer 5 with our client located in Redmond, WA. This role is Hybrid with 2-3 Days/Week onsite.
Job Description:
- The Purpose of the Team: We are working on a project, we are developing next generation version of that chip.
- Selling Points: The industry is turning towards AI & the fact that we are working on the AI chip is probably going to be a big plus for many people.
- Good face to face collaboration; we solve a lot of issues and we all always look for better ways to solve problem instead of a, you know, whatever click fixed or anything like that. Looking for design verification engineer.
Job Responsibilities:
- Define verification strategy, requirements, test environments for IP level verification.
- Create test plans and write tests to provide complete features coverage.
- Own verification for complex IPs, including creating test plans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
- Develop and implement technical solutions to complex quality and design challenges.
- Write scoreboards, sequences, constraints, assertions and functional coverage.
- Write make files and scripts for verification infrastructure.
- Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
- Lead small teams of verification engineers and mentor engineers.
- Collaborate with teams across sites and geographies.
- Typical task breakdown and operating rhythm: 2 hours meetings. A one-on-one meeting bi-weekly 25% and the rest is technical work.
- Must Have 7+ years' experience with ASIC Design Verification (looking for someone who can make sure everything is correct and on schedule utilizing this skillset).
- Must Have 7+ Years's experience with unit level verification.
- Must Have 7+ Years's experience of experience in UVM library (UVM is at universal verification)
- No Degree required, looking for individuals with relevant experience. Even though the job title says hardware design, they are really looking for a hardware design verification engineer, which is going to be requiring a lot of experience in UVM library, methodology and it's an industry standard.)
- 7+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals
- In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments
- Solid understanding of computer architecture
- Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
- Scripting language such as Python or Perl or shell scripts.
- Prior experience with high performance DMA verification
- Will consider: bachelor's degree in electrical engineering, Computer Engineering, or related field AND 5+ years of technical engineering experience
o OR master's degree in electrical engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field - Best vs. Average:
- A lot of block level verification work experience (goes with unit level verification experience listed in hard skills below)
- Someone who works well with others and has a team-work mindset
Preferred Job Qualification:
- 10+ years of technical engineering experience
- OR bachelor's degree in electrical engineering, Computer Engineering, or related field AND 8+ years of technical engineering experience
- OR master's degree in electrical engineering, Computer Engineering, or related field AND 6+ years of technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience.
- 10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
- Experienced in test plan development to define test cases, checkers, assertions, and functional coverage points.
- Experience in verification of many designs at unit level.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Knowledge of system verilog class, constraints, coverage and assertions.
- Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Proficient in reading, debugging, and/or designing using Verilog languages
Job Details:
- Job Type: Contract
- Location: Redmond, WA (This role is Hybrid with 2-3 Days/Week Onsite).
- Pay Range: $91/hr. to $124.50/hr.
- An offer of employment is contingent on successfully passing a background check, and applicants who do not successfully pass a background check will not be considered for employment
- ITAR obligations are associated with this role, U.S. citizenship, U.S. legal permanent resident status, or protected person status under 8 U.S.C. § 1324b(a) (1), (3) is required.
Benefits Package: Protingent offers competitive salaries, insurance plan options (HDHP plan or POS plan), education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO) and an administered 401k plan.
About Protingent: Protingent is a niche provider of top Engineering and IT talent to Software, Electronics, Medical Device, Telecom, and Aerospace companies nationwide. Protingent exists to make a positive impact and contribution to the lives of others as well as our community by providing relevant, rewarding, and exciting work opportunities for our candidates.
Meet Your Recruiter
Share This Job:
Related Jobs:
About Redmond, WA
Are you sure you want to apply for this job?
Please take a moment to verify your personal information and resume are up-to-date before you apply.