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HW Design Eng. 4 / Analog Custom Layout Designer
1045 La Avenida St Mountain View, CA 94043 US
Job Description
Position Description: Protingent Staffing has an exciting contract HW Design Engineer 4 / Analog Custom Layout Designer opportunity with our client located in Silicon Valley, CA. 100% Remote role (anywhere in US is acceptable).
Job Responsibilities:
- The primary responsibility of this position entails executing IC layout of cutting edge, high-performance, high-speed, low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.
- Using Cadence Virtuoso design tool and flow.
- Will be working on highly analog IPs like analog PLL, DLL, ADC, RX, TX, OTAs, LDO, Bandgap and Bias.
- Layout Design review presentations.
- Layout floor-planning and supervision.
- Physical LVS, DRC, DFM.
- Looking for analog custom layout designer to contribute to the development of the high-speed data interface, serial and parallel I/O, and clock generation / distribution for custom ICs.
- The candidate must have a proven record of laying out high performance analog circuits in state-of-the-art CMOS FINFET process technologies (5nm, 3nm, and beyond) and has successfully placed products into volume production.
- The primary responsibility of this position entails executing IC layout of cutting edge, high-performance, high-speed, low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.
- Key projects: This project involves focuses on voltage and temperature monitors.
Must Have Job Requirements:
- Must have 5+ years’ experience with highly analog IPs like analog PLL, DLL, ADC, RX, TX, OTAs, LDO, Bandgap and Bias.
- Must have 5+ years’ experience with Cadence Virtuoso design tool and flow.
- Must have 5+ years’ experience with deep FinFET like 3 nanometer or anything 5 nanometer or below.
- 5-7 overall years of experience in the field.
- A degree is required to be eligible for this role.
- Detailed orientated of EDA tools for Cadence, Mentor and Synopsys. Experience with floor planning, block level routing and large macro level assembly.
- Knowledge of analog design and layout guidelines and high-speed IO.
- 5+ years of experience in high performance analog layout in advanced FINFET CMOS process, 3nm preferred,
- Detailed knowledge of EDA tools for Cadence, Mentor and Synopsys.
- Having experience with layout of high-performance analog blocks such as VCOs, chargepump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references, etc. is desired.
- Experience with floor planning, block level routing and large macro level assembly.
Job Details:
- Job Type: Contract
- Location: Remote.
- Pay Range: $84/hr. to $115/hr.
- An offer of employment is contingent on successfully passing a background check, and applicants who do not successfully pass a background check will not be considered for employment.
Benefits Package: Protingent offers competitive salaries, insurance plan options (HDHP plan or POS plan), education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO) and an administered 401k plan.
About Protingent: Protingent is a niche provider of top Engineering and IT talent to Software, Electronics, Medical Device, Telecom, and Aerospace companies nationwide. Protingent exists to make a positive impact and contribution to the lives of others as well as our community by providing relevant, rewarding, and exciting work opportunities for our candidates.