Sr. VHDL Designer
Milpitas, California | Contract
Position Title: Sr. VHDL Designer
Position Description: Protingent Staffing has an exciting opportunity with our client in San Jose, CA
There exists a timing control subassembly in the Q304i which manages the drive to the AOM/Q Switch. This assembly incorporates an Altera Cyclone IV FPGA which has substantial unused capability. The intent is to leverage the existing architecture to support new diagnostic functions. These new diagnostic functions center around timing measurements mostly in the 10 to 300ns range. There will be two high speed timers feeding 4 registers. Each register is readable through a proprietary bus structure by the host processor (register/bus structure preexisting).
Other control and status registers are also required, as is some limited processing (averaging) and data “ gating” (ignoring measurements during invalid data periods). There is a third timer that measures intervals in the 5 to 50us range, which is used to identify invalid data periods. A fourth timer is used for long interval timing up to ~ 1 second. There will also be some incidental combinatorial logic.
The existing VHDL design is not to be modified (added registers notwithstanding). Any/all changes, however minor, must be reviewed and explicitly approved by us. Additionally, the design must be verified using the test bench provided by us (the test bench covers the preexisting code, but not the code to be developed under this spec.) The engineer for the preexisting design (both HW and VHDL) is available for consultation, but will not be the principal contact. The preexisting VHDL design was implemented using Quartus 11.1 and will be provided.
- A register architecture is already part of the preexisting design.
- Registers are indirectly addressed by the host (existing structure) and new registers for new functions will start at 0x20 (and not exceed 0x7F).
- Multibyte registers span multiple addresses
- Each byte is 8 bits, with any functional value limited to 1? 4 bytes
- Details of sign, scaling, casting, and use of each register are detailed below.
- A preexisting 40.68MHz clock will be used to generate a 999.6MHz clock (PLL: 172/7) which is used for all timing high speed measurements.
- A preexisting 22MHz clock will be used to generate a 1kHz clock (1/22, 000) for long interval timing.
Benefits Package: Protingent offers competitive salary, 100% paid health insurance, education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO) and an administered 401k plan.
About Protingent: Protingent is a niche provider of top Engineering and IT talent to Software, Electronics, Medical Device, Telecom and Aerospace companies nationwide. Protingent exists to make a positive impact and contribution to the lives of others as well as our community by providing relevant, rewarding and exciting work opportunities for our candidates.