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Design Verification Engineer

Santa Clara, California | Direct Hire

Post Date: 05/30/2017 Job ID: 16981 Industry: Engineering

Position Title: Design Verification Engineer

Position Description:  Protingent Staffing has an exciting opportunity with our client in Santa Clara, CA

Central to our client’ s mission is a highly programmable chip. As part of the verification team, you will be responsible for independently creating leading-edge constrained-random verification environments and using them to drive functional correctness of innovative SoCs.

Minimum Requirements:
  • BS and/or MS in Computer Science or equivalent degree
  • 8+ years of experience in ASIC/SoC verification with SV/UVM environments
  • In-depth knowledge of verification flows
  • Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
  • Team player with excellent communication skills and the desire to take on diverse challenges

Additional Success Factors:
  • Advanced knowledge of CPU & SoC architecture/design
  • Experience in verifying data center protocols such as Ethernet, TCP/IP and other communication protocols
  • Knowledge of formal verification, hardware emulation
  • Experience with security
  • Startup experience

About Protingent:  Protingent is a niche provider of top Engineering and IT talent to Software, Electronics, Medical Device, Telecom and Aerospace companies nationwide. Protingent exists to make a positive impact and contribution to the lives of others as well as our community by providing relevant, rewarding and exciting work opportunities for our candidates.

Gazelle Medina


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