Design Verification Engineer
San Diego, California | Contract
Position Title: Design Verification Engineer
Position Description: Protingent Staffing has an exciting opportunity with our client in San Diego, CA.
- Developing of test benches in UVM methodologies
- Calling c model function using DPI from test bench
- Developing random test bench
- Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.
- Develop, maintain and publish verification specifications
- Analyze and debug simulation failures
- Generates code coverage and functional coverage report
- Run gate level simulation and debug them
- Developing scripts for simulation and regression flow
- Minimum of 8+ years’ experience in Verification with a leading chipset company is a primary requirement
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators like Incisive and VCS, and waveform viewer like Verdi
- Fluent in verification methodologies such as UVM, HVL languages such as System Verilog,
- Knowledge of OOP is required
- Knowledge of perl or python is must
- Strong problem solving skill to quickly identify
Benefits Package: Protingent offers competitive salary, 100% paid health insurance, education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO) and an administered 401k plan.
About Protingent: Protingent is a niche provider of top Engineering and IT talent to Software, Electronics, Medical Device, Telecom and Aerospace companies nationwide. Protingent exists to make a positive impact and contribution to the lives of others as well as our community by providing relevant, rewarding and exciting work opportunities for our candidates.